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[AK5388]
= Preliminary =
AK5388
120dB 24-bit 192kHz 4-Channel ADC
GENERAL DESCRIPTION The AK5388 is a 24bit, 216kHz sampling 4-channel A/D converter for high-end audio systems. The modulator in the AK5388 uses AKM's Enhanced Dual Bit architecture, enabling the AK5388 realizes to realize high accuracy and low cost. The AK5388 achieves 120dB dynamic range and -105dB THD+N, and an optional mono mode extends dynamic range to 121dB. The AK5388's digital filter features a modified FIR architecture that minimizes group delay while maintaining excellent linear phase response. So the device is suitable for professional audio applications including recording, sound reinforcement, effects processing, sound cards, and high-end A/V receivers. The AK5388 is available in 44pin LQFP package. FEATURES Sampling Rate: 8kHz ~ 216kHz Full Differential Inputs S/(N+D): 105dB DR, S/N: 120dB(Mono Mode: 123dB) Short Delay Digital Filter (GD=12.6/fs) * Passband: 0~21.648kHz (@fs=48kHz) * Ripple: 0.01dB * Stopband: 80dB Digital HPF Power Supply: 4.75 ~ 5.25V(Analog), 3.0 ~ 3.6V(Digital) Output format: 24bit MSB justified, I2S or TDM Cascade TDM I/F: 8ch/48kHz, 4ch/96kHz, 4ch/192kHz Master & Slave Mode Overflow Flag Power Dissipation: TBD mW (@fs=48kHz) Package: 44pin LQFP
AVDD1 AVSS1 AVDD2 AVSS2 DVDD1 DVSS1 Modulator Modulator Modulator Modulator DVDD2 DVSS2 BVSS
LIN1+ LIN1RIN1+ RIN1LIN2+ LIN2RIN2+ RIN2VCOM1 VCOM2
Decimation Filter Decimation Filter Decimation Filter Audio Interface
LRCK BICK SDTO1 SDTO2 TDMIN M/S DIF TDM0 TDM1 HPF MONO
Decimation Filter
Voltage Reference Clock Divider VRP1 VRL1 VRP2 VRL2 MCLK
OVF
PDN
CKS0 CKS2 CKS2
Rev. 0.3 -1-
2007/10
[AK5388]
Ordering Guide
AK5388EQ AKD5388 -10 ~ +70C 44pin LQFP (0.8mm pitch) Evaluation Board for AK5388
Pin Layout
AVDD2
TEST2
MONO 24
RIN2+
DVDD
HPFE
RIN2-
VSS6
VSS5
VSS4
33
32
31
30
29
28
27
26
25
23
DIF
VREFP2 VREFL2 VCOM2 LIN2+ LIN2TEST3 RIN1RIN1+ VCOM1 VREFL1 VREFP1
34 35 36 37 38 39 40 41 42 43 44 10 3 2 5 6 11 1 4 7 8 9 Top View
22 21 20
TDM1 TDM0 TDMIN OVF SDTO2 SDTO1 VSS3 DVDD LRCK BICK MCLK
AK5388EQ
19 18 17 16 15 14 13 12
TEST1
CKS0
CKS1
AVDD1
Rev. 0.3 -2-
LIN1+
CKS2
VSS1
VSS2
M/SN
LIN1-
PDN
2007/10
[AK5388]
PIN / FUNCTION
No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Pin Name LIN1+ LIN1- VSS1 AVDD1 TEST1 VSS2 CKS0 CKS1 CKS2 PDN M/SN MCLK BICK LRCK DVDD VSS3 SDTO1 SDTO2 OVF TDMIN TDM0 TDM1 DIF MONO HPFE DVDD VSS4 VSS5 I/O I I I I I I I I I I/O I/O O O O I I I I I I Function ADC1 Lch Positive Analog Input Pin ADC1 Lch Negative Analog Input Pin Ground Pin Analog Power Supply Pin, 4.75 5.25V Test Pin (Connected to VSS) Ground pin Clock Mode Select #0 Pin Clock Mode Select #1 Pin Clock Mode Select #2 Pin Power-Down Mode Pin When "L", the circuit is in power-down mode. The AK5388should always be reset upon power-up. Master/Slave mode Select Pin "L": Slave mode, "H": Master mode Master Clock Input Pin Audio Serial Data Clock Pin "L" Output in Master Mode at Power-down mode. Output Channel Clock Pin "L" Output in Master Mode at Power-down mode. Digital Power Supply Pin, 3.0 3.6V Ground Pin ADC1 Audio Serial Data Output Pin "L" Output at Power-down mode. ADC2 Audio Serial Data Output Pin "L" Output at Power-down mode. Analog Input Overflow Detect Pin This pin goes to "H" if any analog inputs overflows. "L" Output at Power-down mode. TDM Data Input Pin TDM I/F Format Enable Pin "L" : Normal Mode, "H" : TDM Mode TDM I/F BICK Frequency Select Pin "L" : Normal Mode, "H" : TDM Mode Audio Interface Format Pin "L": 24BitMSB justified, "H": 24BitI2S Compatible Stereo/Mono mode Select Pin "L": Stereo mode, "H": Mono mode HPF Enable Pin "L": Disable, "H" Enable Digital Power Supply Pin, 3.0 3.6V Ground Pin Ground pin
Rev. 0.3 -3-
2007/10
[AK5388]
No. Pin Name 29 TEST2 30 AVDD2 31 VSS6 32 RIN2- 33 RIN2+ 34 VREFP2 35 VREFL2 36 37 38 39 40 41 42 43 44 VCOM2 LIN2+ LIN2- TEST3 RIN1- RIN1+ VCOM1 VREFL1 VREFP1
I/O I I I I I O I I I I I O I I
Function Test Pin (Connected to VSS) Analog Power Supply Pin, 4.75 5.25V Ground Pin ADC2 Rch Negative Analog Input Pin ADC2 Rch Positive Analog Input Pin ADC2 High Level Voltage Reference Input Pin ADC2 Low Level Voltage Reference Input Pin Common Voltage Output Pin, (AVDD2)/2 Normally connected to AVSS2 with a 0.1F ceramic capacitor in parallel with an electrolytic capacitor less than 2.2F. ADC2 Lch Positive Analog Input Pin ADC2 Lch Negative Analog Input Pin Test Pin (Connected to VSS) ADC1 Rch Negative Analog Input Pin ADC1 Rch Positive Analog Input Pin Common Voltage Output Pin, (AVDD1)/2 Normally connected to AVSS1 with a 0.1F ceramic capacitor in parallel with an electrolytic capacitor less than 2.2F. ADC1 Low Level Voltage Reference Input Pin ADC1 High Level Voltage Reference Input Pin
Note: All digital input pins should not be left floating.
Rev. 0.3 -4-
2007/10
[AK5388]
Handling of Unused Pin
The unused I/O pins should be processed appropriately as below. Classification Analog Digital Pin Name LIN+, LIN- RIN+, RIN- VREFLP1/2, VREFL1/2 OVF TEST1/2/3 Setting These pins should be connected to AVSS. These pins should be connected to AVSS. These pins should be connected to AVDD. This pin should be open. This pin should be connected to DVSS.
ABSOLUTE MAXIMUM RATINGS
(VSS1-6=0V; Note 1) Parameter Power Supplies: Analog Digital Digital Output Buffer Symbol AVDD1/2 DVDD1 DVDD2 IIN VINA VIND Ta Tstg min -0.3 -0.3 -0.3 - -0.3 -0.3 -10 -65 max 6.0 6.0 6.0 10 AVDD+0.3 DVDD+0.3 70 150 Units V V V mA V V C C
Input Current, Any Pin Except Supplies Analog Input Voltage (Note 2) Digital Input Voltage (Note 3) Ambient Temperature (power applied) Storage Temperature
Note 1. All voltages with respect to ground. Note 2. VREFP1, VREFP2, VREFL1, VREFL2, AINL1/2+, AINL1/2-, AINR1/2+ and AINR1/2- pins Note 3. PDN, CKS0, CKS1, CKS2, TDMIN, MCLK, BICK, LRCK, DIF, TDM0, TDM1, HPFE, MONO and TST1/2/3 pins
WARNING: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes.
Rev. 0.3 -5-
2007/10
[AK5388]
RECOMMENDED OPERATING CONDITIONS
(VSS1-6=0V; Note 1) Parameter Power Supplies: (Note 4) Voltage Reference (Note 7) Analog Digital "H" voltage Reference (Note 5) "L" voltage reference (Note 6) (VREFP1/2) - (VREFL1/2) Symbol AVDD1/2 DVDD VREFP1/2 VREFL1/2 VREF min 4.75 3.0 AVDD-0.5 VSS AVDD-0.5 typ 5.0 3.3 max 5.25 3.6 AVDD AVDD Units V V V V V
Note 1. All voltages with respect to ground. Note 4. The power up sequence between AVDD and DVDD is not critical. Note 5. VREFP1 pin, VREFP2 pin Note 6. VREFL1 pin, VREFL2 pin Note 7. VREFL- and VREFR- pins should be connected to AVSS pin. Analog input voltage scales with voltage of {(VREFP) - (VREFL)}. Vin (typ, @ 0dB) = 2.9 x {(VREF+) - (VREF-)} / 5 [V].
WARNING: AKEMD assumes no responsibility for the usage beyond the conditions in this datasheet.
Rev. 0.3 -6-
2007/10
[AK5388]
ANALOG CHARACTERISTICS (Ta = 25C; AVDD1/2=5.0V; DVDD1/2=3.3V; VSS1-6=0V; VREFP1=VREFP2=AVDD, VREFL1 = VREFL2 = VSS; fs=48kHz, 96kHz, 192kHz; BICK=64fs; Signal Frequency=1kHz; 24bit Data; Measurement frequency=10Hz 20kHz at fs = 48kHz, 40Hz 40kHz at fs = 96kHz, 40Hz 40kHz at fs = 192kHz; unless otherwise specified) Parameter min typ max Units Analog Input Characteristics: Resolution 24 Bits Input Voltage (Note 8) 2.7 2.9 3.1 Vpp -1dBFS TBD 105 dB S/(N+D) fs=48kHz -20dBFS 95 dB BW=20kHz -60dBFS 55 dB -1dBFS TBD 102 dB fs=96kHz -20dBFS 90 dB BW=40kHz -60dBFS 50 dB -1dBFS 102 dB fs=192kHz -20dBFS 90 dB BW=40kHz -60dBFS 50 dB Stereo Mode Dynamic Range TBD 120 dB Mono Mode (-60dBFS with A-weighted) 123 Stereo Mode S/N TBD 120 dB Mono Mode (A-weighted) 123 Input Resistance TBD 4.7 k Interchannel Isolation TBD 120 dB Interchannel Gain Mismatch 0.1 TBD dB Power Supply Rejection (Note 9) 50 dB Power Supplies Power Supply Current Normal Operation (PDN pin = "H") mA TBD 88 AVDD1/2 mA TBD 13 DVDD (fs=48kHz) mA TBD 23 DVDD (fs=96kHz) mA TBD 20 DVDD (fs=192kHz) Power down mode (PDN pin = "L") (Note 10) A TBD 10 AVDD+DVDD
Note 8. This value is (LIN+)-(LIN-) and (RIN+)-(RIN-). Input voltage is proportional to VREF voltage. Vin = 0.58 x VREF1/2 (Vpp). Note 9. PSR is applied to AVDD1/2 and DVDD with 1kHz, 20mVpp. The VREFP1 and VREFP2 pins held a constant voltage. Note 10. All digital input pins are held DVDD or VSS3/4.
Rev. 0.3 -7-
2007/10
[AK5388]
FILTER CHARACTERISTICS (fs=48kHz) (Ta=25C; AVDD1/2=4.75 5.25V; DVDD=3.0 3.6V; DFS1 = "L", DFS0 = "L") Parameter Symbol min typ ADC Digital Filter (Decimation LPF): Passband (Note 11) -0.01dB PB 0 -0.1dB 22.0 -3.0dB 23.8 -6.0dB 24.4 Stopband SB 27.9 Passband Ripple PR Stopband Attenuation SA 80 Group Delay (Note 12) GD 12.6 Group Delay Distortion GD 0.01 ADC Digital Filter (HPF): Frequency Response (Note 11) -3dB FR 1.0 -0.1dB 6.5
max 21.6 0.01
Units kHz kHz kHz kHz kHz dB dB 1/fs s Hz Hz
FILTER CHARACTERISTICS (fs=96kHz) (Ta=25C; AVDD1/2=4.75 5.25V; DVDD=3.0 3.6V; DFS1 = "L", DFS0 = "H") Parameter Symbol min typ max Units ADC Digital Filter (Decimation LPF): Passband (Note 11) -0.01dB PB 0 43.3 kHz -0.1dB 44.2 kHz -3.0dB 47.6 kHz -6.0dB 48.9 kHz Stopband SB 55.9 kHz Passband Ripple PR 0.01 dB Stopband Attenuation SA 80 dB Group Delay (Note 12) GD 12.6 1/fs Group Delay Distortion GD 0.013 s ADC Digital Filter (HPF): Frequency Response (Note 11) -3dB FR 1.0 Hz -0.1dB 6.5 Hz Note 11. The passband and stopband frequencies scale with fs. The reference frequency of these responses is 1kHz. Note 12. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the setting of 24bit data both channels to the ADC output register for ADC.
Rev. 0.3 -8-
2007/10
[AK5388]
FILTER CHARACTERISTICS (fs=192kHz) (Ta=25C; AVDD1/2=4.75 5.25V; DVDD=3.0 3.6V; DFS1 = "H", DFS0 = "L") Parameter Symbol min typ ADC Digital Filter (Decimation LPF): Passband (Note 11) -0.01dB PB -0.1dB 83.4 -3.0dB 99.9 -6.0dB 106.5 Stopband SB 141.1 Passband Ripple PR Stopband Attenuation SA 80 Group Delay (Note 12) GD 9.8 Group Delay Distortion GD 0 ADC Digital Filter (HPF): Frequency Response (Note 11) -3dB FR 1.0 -0.1dB 6.5
max 0.08
Units kHz kHz kHz kHz kHz dB dB 1/fs s Hz Hz
Note 12. The passband and stopband frequencies scale with fs. The reference frequency of these responses is 1kHz. Note 13. The calculated delay time induced by digital filtering. This time is from the input of an analog signal to the setting of 24bit data both channels to the ADC output register for ADC.
DC CHARACTERISTICS (Ta=25C; AVDD1/2=4.75 5.25V; DVDD=3.0 3.6V) Parameter Symbol min High-Level Input Voltage VIH 70%DVDD Low-Level Input Voltage VIL High-Level Output Voltage (Iout=-400A) VOH DVDD-0.4 Low-Level Output Voltage (Iout=400A) VOL Input Leakage Current Iin -
typ -
Max 30%DVDD 0.4 10
Units V V V V A
Rev. 0.3 -9-
2007/10
[AK5388]
SWITCHING CHARACTERISTICS (Ta=25C; AVDD1/2=4.75 5.25V; DVDD=3.0 3.6V; CL=20pF) Parameter Symbol min Master Clock Timing 2.048 fCLK Master Clock 256fs: 0.4fCLK tCLKL Pulse Width Low 0.4fCLK tCLKH Pulse Width High 3.072 fCLK 384fs: 0.4fCLK tCLKL Pulse Width Low 0.4fCLK tCLKH Pulse Width High 4.096 fCLK 512fs: 0.4fCLK tCLKL Pulse Width Low 0.4fCLK tCLKH Pulse Width High 6.144 fCLK 768fs: 0.4fCLK tCLKL Pulse Width Low 0.4fCLK tCLKH Pulse Width High LRCK Timing (Slave Mode) Normal mode (TDM1="L", TDM0="L") LRCK Frequency fs 8 Duty Cycle Duty 45 TDM256 MODE (TDM1="L", TDM0="H") LRCK Frequency fs 8 "H" time tLRH 1/256fs "L" time tLRL 1/256fs TDM128 MODE (TDM1="H", TDM0="H") LRCK Frequency fs 8 "H" time tLRH 1/128fs "L" time tLRL 1/128fs LRCK Timing (Master Mode) Normal mode (TDM1="L", TDM0="L") LRCK Frequency fs 8 Duty Cycle Duty TDM256 MODE (TDM1="L", TDM0="H") LRCK Frequency fs 8 "H" time (Note 13) tLRH TDM128 MODE (TDM1="H", TDM0="H") fs 8 LRCK Frequency tLRH "H" time (Note 13)
Note 13. "L" time at I2S format
typ 12.288
max 27.648
Units MHz ns ns MHz ns ns MHz ns ns MHz ns ns
18.432
36.864
24.576
27.648
36.864
36.864
216 55 54
kHz % kHz ns ns kHz ns ns
216
216 50 54 1/8fs 216 1/4fs
kHz % kHz ns kHz ns
Rev. 0.3 - 10 -
2007/10
[AK5388]
Parameter Audio Interface Timing (Slave mode) Normal mode (TDM1="L", TDM0="L") BICK Period Normal Speed Mode Double , Quad Speed Mode BICK Pulse Width Low Pulse Width High LRCK Edge to BICK "" (Note 14) BICK "" to LRCK Edge (Note 14) LRCK to SDTO1/2 (MSB) (Except I2S mode) BICK "" to SDTO1/2 TDM256 mode (TDM1="L", TDM0="H") BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK "" (Note 14) BICK "" to LRCK Edge (Note 14) BICK "" to SDTO1/2 TDM128 mode (TDM1="H", TDM0="H") BICK Period BICK Pulse Width Low Pulse Width High LRCK Edge to BICK "" (Note 14) BICK "" to LRCK Edge (Note 14) BICK "" to SDTO1 (Note 15) Audio Interface Timing (Master mode) Normal mode (TDM1="L", TDM0="L") BICK Frequency BICK Duty BICK "" to LRCK BICK "" to SDTO1/2 TDM256 mode (TDM1="L", TDM0="H") BICK Frequency BICK Duty (Note 16) BICK "" to LRCK BICK "" to SDTO1/2 TDM128 mode (TDM1="H", TDM0="H") BICK Frequency BICK Duty BICK "" to LRCK BICK "" to SDTO1 (Note 15) Power-Down & Reset Timing PDN Pulse Width (Note 17) PDN "" to SDTO1/2 valid (Note 18)
Symbol
min
typ
max
Units
TBCK TBCK tBCKL tBCKH tLRB tBLR tLRS tBSD tBCK tBCKL tBCKH tLRB tBLR tBSD tBCK tBCKL tBCKH tLRB tBLR tBSD
1/128fs 1/64fs 32 32 20 20 20 20 1/256fs 16 16 16 16 10 1/128fs TBD TBD TBD TBD TBD
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
fBCK dBCK tMBLR tBSD fBCK dBCK tMBLR tBSD fBCK dBCK tMBLR tBSD tPD tPDV
64fs 50 -20 -20 256fs 50 -12 -20 128fs 50 -TBD -TBD 150 516 TBD TBD 12 20 20 20
Hz % ns ns Hz % ns ns Hz % ns ns ns 1/fs
Rev. 0.3 - 11 -
2007/10
[AK5388]
Note 14. BICK rising edge must not occur at the same time as LRCK edge. Note 15. SDTO2 output is fixed to "L". Note 16. This value is MCLK=512fs. Duty cycle is not guaranteed when MCLK=256fs/384fs. Note 17. The AK5388 can be reset by bringing the PDN pin = "L". Note 18. This cycle is the number of LRCK rising edges from the PDN pin = "H".
Timing Diagram
1/fCLK VIH VIL tCLKH tCLKL
MCLK
1/fs VIH VIL
LRCK
tBCK VIH VIL tBCKH tBCKL
BICK
Figure 1. Clock Timing (TDM0 pin = "L")
1/fCLK VIH VIL tCLKH tCLKL
MCLK
1/fs VIH VIL tLRH tLRL
LRCK
tBCK VIH VIL tBCKH tBCKL
BICK
Figure 2. Clock Timing (TDM0 pin = "H")
Rev. 0.3 - 12 -
2007/10
[AK5388]
VIH LRCK VIL tBLR tLRB VIH BICK VIL tLRS tBSD
SDTO
Figure 3. Audio Interface Timing (Slave mode, TDM0 pin = "L") Note: SDTO shows SDTO1 and SDTO2.
50%DVDD
VIH LRCK VIL tBLR tLRB VIH BICK VIL tBSD
SDTO1
50%DVDD
tTDMS VIH TDMIN VIL
Figure 4. Audio Interface Timing (Slave mode, TDM0 pin = "H")
Rev. 0.3 - 13 -
2007/10
[AK5388]
VIH LRCK VIL tBLR tLRB VIH BICK VIL tBSD
SDTO1
50%DVDD
Figure 5. Audio Interface Timing (Slave mode, TDM0 pin = "H" ,TDM1 pin = "H" ,8KHz fs < 108KHz)
VIH LRCK VIL tBLR tLRB VIH BICK VIL tBSS tBSH
SDTO1
DATA
50%DVDD
Figure 6. Audio Interface Timing (Slave mode, TDM0 pin = "H",TDM1 pin = "H" ,108KHz < fs 216KHz)
Rev. 0.3 - 14 -
2007/10
[AK5388]
LRCK
50%DVDD
tMBLR
dBCK 50%DVDD
BICK
tBSD
SDTO
Figure 7. Audio Interface Timing (Master mode)
50%DVDD
VIH PDN VIL tPD tPDV
SDTO
50%DVDD
Figure 8. Power Down & Reset Timing
Note: SDTO shows SDTO1 and SDTO2.
Rev. 0.3 - 15 -
2007/10
[AK5388]
OPERATION OVERVIEW
System Clock
MCLK (256fs/384fs/512fs), BICK (48fs) and LRCK (fs) clocks are required in slave mode. The LRCK clock input must be synchronized with MCLK, however the phase is not critical. Table 1 shows the relationship of typical sampling frequency and the system clock frequency. MCLK frequency is selected by CKS1-0 pins as shown in Table 2. Since the AK5388 includes a phase detection circuit for LRCK, the AK5388 is reset automatically when the synchronization is out of phase after changing the clock frequencies. All external clocks (MCLK, BICK and LRCK) must be present unless the PDN pin = "L". If these clocks are not provided, the AK5388 may draw excess current due to its use of internal dynamically refreshed logic. If the external clocks are not present, place the AK5388 in power-down mode (PDN pin = "L"). In master mode, the master clock (MCLK) must be provided unless PDN pin = "L". fs 32kHz 48kHz 96kHz 192kHz MCLK 256fs 384fs 8.192MHz 12.288MHz 12.288MHz 18.432MHz 24.576MHz N/A N/A N/A
128fs N/A N/A N/A 24.576MHz
192fs N/A N/A N/A 36.864MHz
512fs 768fs 16.384MHz 24.576MHz 24.576MHz 36.864MHz N/A N/A N/A N/A (N/A: Not available)
Table 1. System Clock Example (Slave Mode) fs 32kHz 48kHz 96kHz 192kHz MCLK 256fs 384fs 8.192MHz 12.288MHz 12.288MHz 18.432MHz 24.576MHz 36.864MHz N/A N/A
128fs N/A N/A N/A 24.576MHz
192fs N/A N/A N/A 36.864MHz
512fs 768fs 16.384MHz 24.576MHz 24.576MHz 36.864MHz N/A N/A N/A N/A (N/A: Not available)
Table 2. System Clock Example (Master Mode) fs 32kHz 48kHz 96kHz 192kHz MCLK 256fs 384fs N/A N/A N/A N/A 24.576MHz 36.864MHz N/A N/A
128fs N/A N/A N/A 24.576MHz
192fs N/A N/A N/A 36.864MHz
512fs 768fs 16.384MHz 24.576MHz 24.576MHz 36.864MHz N/A N/A N/A N/A (N/A: Not available)
Table 3. System Clock Example (Auto Mode)
Rev. 0.3 - 16 -
2007/10
[AK5388]
M/S Pin
L
H
CKS2 pin L L L L H H H H L L L L H H H H
CKS0 pin L L H H L L H H L L H H L L H H
CKS0 pin L H L H L H L H L H L H L H L H
MCLK Frequency 128fs (108KHz < fs 216KHz) 192fs (108KHz < fs 216KHz) 256fs (8KHz fs 54KHz) 256fs (54KHz < fs 108KHz) Auto (8KHz fs 216KHz) 384fs (8KHz fs 54KHz) 512fs (8KHz < fs 54KHz) 768fs (8KHz fs 54KHz) 128fs (108KHz < fs 216KHz) 192fs (108KHz < fs 216KHz) 256fs (8KHz fs 54KHz) 256fs (54KHz < fs 108KHz) 384fs (54KHz fs 108KHz) 384fs (8KHz fs 54KHz) 512fs (8KHz < fs 54KHz) 768fs (8KHz fs 54KHz)
Table 4. MCLK Frequency
When changing MCLK frequency in master/slave mode, the AK5388 should reset by PDN pin = "L". (ex. 12.288MHz(@fs=48kHz) at CKS1 pin = CKS0 pin = "L".
Audio Interface Format
12 different audio data interface formats can be selected using the TDM1-0, M/S and DIF pins as shown in Table 5. The audio data format can be selected by the DIF pin. In all formats the serial data is MSB-first, 2's compliment format. The SDTO1/2 is clocked out on the falling edge of BICK. In normal mode, Mode 0-1 are the slave mode, and BICK is available up to 128fs at fs=48kHz. BICK outputs 64fs clock in Mode 2-3. In TDM256 mode, all of the ADC's serial data (four channels) is output from the SDTO1 pins. The SDTO2 output is fixed to "L". BICK should be fixed to 256fs. In slave mode, "H" time and "L" time of LRCK should be at least 1/256fs. In master mode, "H" time ("L" time at I2S mode) of LRCK is 1/8fs typical. TDM256 mode does not support 96kHz sampling. In TDM128 mode, all of the ADC's serial data (four channels) is output from the SDTO1 pin. The SDTO2 output is fixed to "L". BICK should be fixed to 128fs. In the slave mode, "H" time and "L" time of LRCK should be at least 1/128fs. In master mode, "H" time ("L" time at I2S mode) of LRCK is 1/4fs typical. TDM128 mode supports up to 192kHz sampling.
Rev. 0.3 - 17 -
2007/10
[AK5388]
Mode 0 1 2 3 4 5 6 7 8 9 10 11 12
TDM1
TDM0
Normal
L
TDM256
L
TDM128 N/A
H H
LRCK I/O L 24bit, MSB justified H/L I L 2 H 24bit, I S Compatible L/H I L L 24bit, MSB justified H/L O H H 24bit, I2S Compatible L/H O L 24bit, MSB justified I L H 24bit, I2S Compatible I H L 24bit, MSB justified O H O H 24bit, I2S Compatible L 24bit, MSB justified I L 2 H 24bit, I S Compatible I H L 24bit, MSB justified O H O H 24bit, I2S Compatible L N/A N/A N/A N/A N/A Table 5. Audio Interface Formats (N/A: Not available) M/S DIF SDTO
BICK 48-128fs 48-128fs 64fs 64fs 256fs 256fs 256fs 256fs 128fs 128fs 128fs 128fs N/A I/O I I O O I I O O I I O O N/A
LRCK
0 1 2 12 13 14 24 25 31 0 1 2 12 13 14 24 25 31 0 1
BICK(64fs) SDTO1/2(o)
23 22 12 11 10 0 23 22 12 11 10 0 23
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 9. Mode 0, 2 Timing (Normal mode, MSB justified)
LRCK
0 1 2 3 23 24 25 26 29 30 31 0 1 2 3 23 24 25 26 29 30 31 0 1
BICK(64fs) SDTO1/2(o)
23 22 2 1 0 23 22 2 1 0
23:MSB, 0:LSB
Lch Data
Rch Data
Figure 10. Mode 1, 3 Timing (Normal mode, I2S Compatible)
256 BICK
LRCK (Mode 6) LRCK (Mode 4) BICK (256fs) SDTO1
23 22 0 23 22 0 23 22 0 23 22 0 23 22
L1
32 BICK
R1
32 BICK
L2
32 BICK
R2
32 BICK
Figure 11. Mode 4, 6 Timing (TDM256 mode, MSB justified)
Rev. 0.3 - 18 -
2007/10
[AK5388]
256 BICK
LRCK (Mode 7) LRCK (Mode5) BICK (256fs) SDTO1
23 0 23 0 23 0 23 0 23
L1
32 BICK
R1
32 BICK
L2
32 BICK
R2
32 BICK
Figure 12. Mode 5, 7 Timing (TDM256 mode, I2S Compatible)
128 BICK
LRCK (Mode 10) LRCK (Mode 8) BICK (128fs) SDTO1
23 22 0 23 22 0 23 22 0 23 22 0 23 22
L1
32 BICK
R1
32 BICK
L2
32 BICK
R2
32 BICK
Figure 13. Mode 8, 10 Timing (TDM128 mode, MSB justified)
128 BICK
LRCK (Mode 11) LRCK (Mode 9) BICK (128fs) SDTO1
23 22 0 23 22 0 23 22 0 23 22 0 23
L1
32 BICK
R1
32 BICK
L2
32 BICK
R2
32 BICK
Figure 14. Mode 9, 11 Timing (TDM128 mode, I S Compatible)
2
Rev. 0.3 - 19 -
2007/10
[AK5388]
Digital High Pass Filter (HPF)
The ADC has a digital high pass filter for DC offset cancellation. The cut-off frequency of the HPF is 1.0Hz (@fs=48kHz). The HPF is controlled by the HPFE pin. If the HPF setting (ON/OFF) is changed during operation, a click noise occurs due to the change in DC offset. The HPF setting should only be changed when the PDN pin = "L".
Overflow Detection
The AK5388 has an overflow detect function for the analog input. The OVF pin goes to "H" if either channel overflows (more than -0.3dBFS). OVF output for overflowed analog input has the same group delay as the ADC (GD=13/fs=0.27ms@fs=48kHz). OVF is "L" for 516/fs (=10.75ms@fs=48kHz) after the PDN pin = "", and then overflow detection is enabled.
Power Down and Reset
The AK5388 is placed in the power-down mode by bringing PDN pin "L" and the digital filter is also reset at the same time. This reset should always be done after power-up. In the power-down mode, the VCOM is AGND level. An analog initialization cycle starts after exiting the power-down mode. The output data SDTO is valid after 516 cycles of LRCK clock in master mode (517 cycles in slave mode). During initialization, the ADC digital data outputs of both channels are forced to "0". The ADC outputs settle to data correspondent to the input signals after the end of initialization (Settling takes approximately the group delay time). The AK5388 should be reset once by bringing the PDN pin "L" after power-up. The internal timing starts clocking by the rising edge (falling edge at Mode 1) of LRCK after exiting from reset and power down state by MCLK.
(1)
PDN Internal State A/D In (Analog) A/D Out (Digital) Clock In
MCLK,LRCK,SCLK
Normal Operation GD (2)
Power-down
Initialize
Normal Operation GD
Idle Noise
(3) "0"data
"0"data
Idle Noise
(4)
Notes: (1) 517/fs in slave mode and 516/fs in master mode. (2) Digital output corresponding to analog input has group delay (GD). (3) A/D output is "0" data in power-down state. (4) When the external clocks (MCLK, SCLK, LRCK) are stopped, the AK5388 should be in the power-down state. Figure 3. Power-down/up sequence example
Rev. 0.3 - 20 -
2007/10
ASAHI KASEI
[AK5388]
Cascade TDM Mode
The AK5388 supports cascading of up to two devices in a daisy chain configuration in TDM256 mode. In this mode, SDTO2 pin of device #1 is connected to TDMIN pin of device #2. The SDTO1 pin of device #2 can output 8-chnnels of TDM data multiplexed with 4-chnnel of TDM data from device #1 and 4-channel of TDM data from device #2. Figure 15 shows a connection example of a daisy chain.
MCLK AK5388 #1 LRCK BICK TDMIN SDTO1 SDTO2 GND 256fs or 512fs 48kHz 256fs
MCLK AK5388 #2 LRCK BICK TDMIN SDTO1 SDTO2 8ch TDM
Figure 15. Cascade TDM Connection Diagram
256 BICK
LRCK BICK(256fs) #1 SDTO1(o)
23 22 0 23 22 0 23 22 0 23 22 0 23 22
L1
32 BICK
R1
32 BICK
L2
32 BICK
R2
32 BICK
#1 SDTO2(o)
23 22
0
23 22
0
23 22
0
23 22
0
L1
32 BICK
R1
32 BICK
L2
32 BICK
R2
32 BICK
#2 TDMIN(i)
23 22
0
23 22
0
23 22
0
23 22
0
L1
32 BICK
R1
32 BICK
L2
32 BICK
R2
32 BICK
#2 SDTO1(o)
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
0
23 22
L1
32 BICK
R1
32 BICK
L2
32 BICK
R2
32 BICK
L1-#1
32 BICK
R1-#1
32 BICK
L2-#1
32 BICK
R2-#1
32 BICK
Figure 16. Cascade TDM Timing
Rev. 0.3 - 21 -
2007/10
ASAHI KASEI
[AK5388]
Mono mode
When the MONO pin is set to "H", the AK5388 is in MONO mode. In the Mono mode, dynamic range and S/N can be improved by approximately 3dB when the same analog signal is inputted to left and right channels. The output data format is to be determined. MONO pin SDTO1/2 Output Data
L Stereo Mode H Mono Mode Table 6. Setup of MONO mode
Rev. 0.3 - 22 -
2007/10
ASAHI KASEI
[AK5388]
SYSTEM DESIGN
Figure 17 and Figure 18 show the system connection diagram. The evaluation board demonstrates application circuits, the optimum layout, power supply arrangements and measurement results.
TBD
Note: - AVSS, BVSS and DVSS of the AK5388 should be distributed separately from the ground of external digital devices (MPU, DSP etc.). - All input pins except pull-down (CKS0, CKS1 and TEST pin) pin should not be left floating. Figure 17. Typical Connection Diagram
TBD
Figure 18. Ground Layout Note: - AVSS BVSS, and DVSS must be connected to the same analog ground plane.
Rev. 0.3 - 23 -
2007/10
ASAHI KASEI
[AK5388]
1. Grounding and Power Supply Decoupling The AK5388 requires careful attention to power supply and grounding arrangements. Alternatively if AVDD and DVDD are supplied separately, the power up sequence is not critical. AVSS, BVSS and DVSS of the AK5388 must be connected to the analog ground plane. System analog ground and digital ground should be connected together near to where the supplies are brought onto the printed circuit board. Decoupling capacitors should be as near to the AK5388 as possible, with the small value ceramic capacitor being the nearest. 2. Voltage Reference Inputs The reference voltage for A/D converter is supplied from VREFL/R pins at AVSS reference. AVSS pin is connected to analog ground and an electrolytic capacitor over 10F parallel with a 0.1F ceramic capacitor between the VREFL/R pins and the AVSS pin eliminate the effects of high frequency noise. It is important that a ceramic capacitor should be as near to the pins as possible. All digital signals, especially clocks, should be kept away from the VREFL/R pins in order to avoid unwanted coupling into the AK5388. No load current may be taken from the VREFL/R pins. VCOM is a signal ground for this device. An electrolytic capacitor (0.22F typical) attached to the VCOM pin eliminates the effects of high frequency noise. No load current may be drawn from the VCOM pin. All signals, especially clocks, should be kept away from the VCOM pin in order to avoid unwanted coupling into the AK5388. 3. Analog Inputs The Analog input signal is differentially supplied into the modulator via the LIN+ (RIN+) and the LIN- (RIN-) pins. The input voltage is the difference between the LIN+ (RIN+) and LIN- (RIN-) pins. The full scale signal on each pin is nominally 2.9Vpp(typ). The AK5388 can accept input voltages from AVSS to AVDD. The ADC output data format is two's complement. The internal HPF removes DC offset. The AK5388 samples the analog inputs at 128fs (6.144MHz@fs=48kHz, Normal Speed Mode). The digital filter rejects noise above the stop band except for multiples of 128fs. The AK5388 includes an anti-aliasing filter (RC filter) to attenuate a noise around 128fs. The AK5388 requires a +5V analog supply voltage. Any voltage which exceeds the upper limit of AVDD+0.3V and lower limit of AVSS-0.3V and any current beyond 10mA for the analog input pins (LIN+/-, RIN+/-) should be avoided. Excessive currents to the input pins may damage the device. Hence input pins must be protected from signals at or beyond these limits. Use caution especially when using 15V for other analog circuits in the system.
Rev. 0.3 - 24 -
2007/10
ASAHI KASEI
[AK5388]
4. External Analog Circuit Examples Figure 19 shows an input buffer circuit example 1. (1st order HPF; fc=0.70Hz, 2nd order LPF; fc=320kHz, gain=-14.5dB). The analog signal is able to input through XLR or BNC connectors. (short JP1 and JP2 for BNC input, open JP1 and JP2 for XLR input). The input level of this circuit is +/-TBDVpp (AK5388: +/-2.9Vpp Typ.). When using this circuit, analog characteristics at fs=48kHz is DR=120dB, S/(N+D)=TBDdB.
4.7k 4.7k Analog In TBDVp VP+
+
620 JP1 Vin+ 68 1n 3.3k Bias
+
91
2.9Vpp AK5388 AIN+
VPNJM5534 XLR
NJM5534
2.2n 620
VA+ 10k Bias + 10k 10 0.1 VA=+5V VP=15V
JP2
68
1n 3.3k
+
91 AK5388 AIN-
Vin-
NJM5534 Bias
2.9Vpp
Figure 19.Input Buffer example1
fin 1Hz 10Hz Frequency Response -1.56dB -0.02dB Table 7. Frequency Response of HPF fin 20kHz 40kHz Frequency Response -0.005dB -0.02dB Table 8. Frequency Response of LPF 6.144MHz -15.6dB
Rev. 0.3 - 25 -
2007/10
ASAHI KASEI
[AK5388]
PACKAGE
44pin LQFP (Unit: mm)
12.800.30 1.70max 00.2 10.00 33 34 23
22 12.800.30 10.00 12
0.80 44 1 0.370.10 11
0.170.05 010
0.600.20 0.15
Material & Lead finish
Package molding compound: Lead frame material: Lead frame surface treatment: Epoxy Cu Solder (Pb free) plate
Rev. 0.3 - 26 -
2007/10
ASAHI KASEI
[AK5388]
MARKING
AK5388EQ XXXXXXX
AKM
1
1) Pin #1 indication 2) Audio 4 pro Logo 3) Date Code: XXXXXXX(7 digits) 4) Marking Code: AK5388 5) AKM Logo
IMPORTANT NOTICE These products and their specifications are subject to change without notice. When you consider any use or application of these products, please make inquiries the sales office of Asahi Kasei EMD Corporation (AKEMD) or authorized distributors as to current status of the products. AKEMD assumes no liability for infringement of any patent, intellectual property, or other rights in the application or use of any information contained herein. Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. AKEMD products are neither intended nor authorized for use as critical componentsNote1) in any safety, life support, or other hazard related device or systemNote2), and AKEMD assumes no responsibility for such use, except for the use approved with the express written consent by Representative Director of AKEMD. As used here: Note1) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. Note2) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. It is the responsibility of the buyer or distributor of AKEMD products, who distributes, disposes of, or otherwise places the product with a third party, to notify such third party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKEMD harmless from any and all claims arising from the use of said product in the absence of such notification.
Rev. 0.3 - 27 -
2007/10

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